1. Field of the Invention
The present invention relates to a semiconductor device including an ESD protective element that prevents a current generated by electrostatic discharge (to be referred to as ESD hereinafter) from flowing in a semiconductor circuit.
2. Description of the Related Art
An ESD protective element recently uses a multi-fingered MOS transistor (interdigital MOS transistor) including a plurality of MOS transistors to ensure the gate width in a predetermined area. It is important in the multi-fingered MOS transistor to uniformly operate the MOS transistors. A known means for implementing the uniform operation is a salicide block technique.
The salicide block technique forms a salicide block having a uniform width between gates and drains to uniformly raise the resistance after the MOS transistors operates, thereby reducing the operation variation between the MOS transistors. However, MOS transistors located near the center far from substrate contacts readily operate. Hence, it is difficult to sufficiently reduce the operation variation between the MOS transistors.
There are the following proposals to solve the above-described problem. A technique of partially changing the gate length has been proposed (e.g., U.S. Pre-Grant Publication No. 2003/0202307A1). In this proposal, however, the characteristics of a transistor itself change as the gate length changes.
There is proposed another technique of partially changing the interval between gates and drain contacts (e.g., Jpn. Pat. Appln. KOKAI Publication No. 7-45829). In this method, however, to change the resistance value in the drain region, the distance between the gates and drains before the change of interval need to be long because the length of the silicide region changes.